The present invention is related to nanoscale electronic circuit interconnections, including memory devices employing nanowire crossbars and defect-tolerant interconnections with electrically distinguishable signal levels between microelectronic circuit elements and nanowires. Nanowire crossbar technologies, and a variety of nanoscale electronic circuits, are discussed in a number of issued U.S. patents and filed U.S. patent applications, including (1) U.S. Pat. No. 6,459,095, entitled “Chemically Synthesized and Assembled Electronic Devices,” issued to James R. Heath et al. on Oct. 1, 2002; (2) U.S. Pat. No. 6,314,019, entitled “Molecular Wire Crossbar Interconnect (MWCI) for Signal Routing and Communications,” issued to Philip J. Kuekes et al. on Nov. 6, 2001; (3) U.S. application Ser. No. 09/280,045, entitled “Molecular Wire Crossbar Logic (MWCL),” filed on Mar. 29, 1999, in the names of Philip J. Kuekes et al.; (4) U.S. Pat. No. 6,128,214, entitled “Molecular Wire Crossbar Memory,” issued to Philip J. Kuekes et al. on Oct. 3, 2000; and (5) U.S. Pat. No. 6,256,767, entitled “Demultiplexer for a Molecular Wire Crossbar Network,” issued to Philip J. Kuekes et al. on Jul. 3, 2001, all assigned to the same assignee as the present application.
Nanowire crossbars provide an enormous increase in device density compared with current, photolithography-produced microelectronic and sub-microelectronic circuitry. However, many alignment and spontaneous defect problems need to be overcome to successfully manufacture electronic devices that include nanoelectronic circuits, including nanowire crossbars. A number of techniques and nanowire-crossbar implementations have been designed to overcome these alignment and defect problems, including configurable, or reprogrammable, nanowire-crossbar implementations that allow defects to be detected and circumvented by programming configurations that provide desired functionality without incorporating defective molecular junctions. These techniques are not needed for current microelectronic circuitry produced by photolithographic techniques, because microelectronic circuits can be assumed, in the current discussion, to be essentially perfect or, more precisely, the defect rate in photolithography-produced microelectronic circuits is so far below the current defect rate in nanoscale electronic circuitry that the comparatively very low defect rate in microelectronic circuitry can be ignored.
Nanoscale electronic circuits need to interface to microelectronic circuitry in order to be incorporated within commercially viable and useful electronic devices. The interface between essentially non-defective microelectronic circuitry and nanoelectronic circuitry is problematic. While various correctly functioning nanoelectronic circuits can be configured from defect-prone nanowire crossbars, these nanoscale circuits need to be interconnected with microelectronic circuits. The relatively high manufacturing-defect rate that occurs in fabricating nanoelectronic devices may produce a yield of usable combination nanoscale/microscale circuits too low to be economically viable. However, it is not feasible to extend existing redundancy-based, defect avoidance strategies designed for nanoscale circuits to microelectronic circuitry through nanoscale-to-microscale interfaces, because these redundancy-based techniques depend on an ability to attempt a measurement of each junction in the nanoscale circuits to determine whether or not the junction is defective. Such individual access to junctions within an interconnection interface would require the interconnection interface to be properly functioning in the first place. In other words, the redundancy-based techniques assume defective nanoscale circuitry components, but rely on an ability to address the components through a properly working interconnection interface. Thus, defects in the interconnection interface result in degradation or complete lack of addressability of interconnection interface components. The interconnection interface may be viewed as a type of bootstrap mechanism that allows defect control in a nanoscale circuit, the components of which are addressed through the bootstrap For example, electronic memories based on nanowire-crossbar-implemented memory-element arrays are attractive with respect to size and power consumption, but are not economically viable using current designs and manufacturing strategies, because defects in the interconnect would make large portions of the memory unaddressable, pushing the effective cost/bit of manufacture to a level too high to be competitive.
Another problem that arises in nanoscale electronics is that the separations between ON and OFF voltage or current states may not be sufficiently large to distinguish between ON and OFF states in the presence of noise and imperfect manufacturing tolerances in certain types of circuits, including in groups of nanowires activated by intersecting address signal lines in demultiplexers and other types of circuits. For binary-logic-based circuitry, an easily detected voltage or current separation between “1,” or ON, and “0,” or OFF, states is needed. In certain types of demultiplexers, for example, one of a large set of nanowires may be addressed by the voltage or current states on a smaller number of address lines that cross the nanowire of interest. If the selected nanowire is designed to have a low, “0,” or, synonymously, OFF state, and the unselected nanowires are designed to have a high, “1,” or, synonymously, ON state, then the voltage or current difference between the selected nanowire and the lowest voltage or lowest current unselected nanowire must be sufficiently large to be easily detected. Unfortunately, the electronic characteristics of nanowire molecular junctions may be difficult to precisely manufacture, leading to leaky diodes, resistors with a wide variation in resistance, and leaky transistors, in turn leading to undesirably narrow differences between ON and OFF states in addressed nanowires.
These same considerations arise in a variety of different types of systems in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes. To date, correct separation of signals into discrete, distinguishable signal-level classes has been largely accomplished by means of precise manufacturing tolerances. However, more recent classes of systems that discriminate between various types of signals are not amenable to sufficiently precise manufacturing, of which nanoscale electronics is but one example. Additional examples include microfluidics-based systems, which may depend on chemical-signal thresholds for which precise manufacture, detection, and operation may be problematic. Additional examples include microelectromechanical (“MEMS”) systems, hybrid electrical systems featuring nanoscale, microscale, and macroscale components, and quantum computing.
For these reasons, designers and manufacturers of nanoscale electronic circuitry, and, in particular, nanoscale electronic memories, have recognized the need for defect-tolerant interconnection within nanoscale circuitry in the interface between microscale and nanoscale circuits. Moreover, designers and manufacturers of nanoscale electronic circuitry have recognized the need for interconnections with distinguishable signal levels between nanowires and address signal lines that select one or a subset of nanowires to have a different voltage or current state than the remaining nanowires.